|CMP / 03Jitter|
It is a common misconception in audio circles that computers are unsuitable for audio because they inevitably exhibit too much jitter. In truth, computer manufacturers routinely deal with jitter tolerances that are very much tighter than those found in audio equipment and use jitter testing equipment measuring in femtoseconds (thousandths of a picosecond) to achieve high bandwidths and low bit-error rates.
Extended listening tests suggested that a cMP transport sending upsampled data via optical Toslink was superior to other methods of driving a DAC and that sound quality improved when the transport provided the master clock. These findings contradict received wisdom. A description of the listening tests, a brief introduction to jitter in digital audio and a report on how the subjective findings were strikingly verified with a series of measurements is presented.
The listening tests
The acid test for subjective sound quality is taken here as meaning listening intently to complete CDs with which the listener is familiar without feeling tired or uninvolved. Procedures such as blind testing and focus groups are of little help in this context and initial impressions that this or that change is for the better (placebo effects) tend to be dispelled over the course of a full CD.
Below are some general impressions for the different test setups. The player used was Foobar2000 and SRC-upsampled 24/96 data were sent to the DAC via a Toslink SPDIF in each case.
Of all the critical parameters in an audio system, a natural ‘bloom’ is possibly the most important – not an artificial bloom which quickly becomes apparent and fatiguing to listen to but one that is slightly understated and never fatiguing, producing a sound that is lifelike and with real ‘presence’. Jitter (and incorrect upsampling) destroy it.
It was the late Julian Dunn who laid the foundations for understanding jitter in audio. Examples of his work, which is most impressive, can readily be found on the web. In the digital audio context, jitter refers to timing errors in the master clock used in DACs and ADCs. Even slight errors cause errors in signal amplitude. The effect can be modelled, simulated and measured. It is either random, which is easy to understand, or deterministic, which is less so.
Deterministic jitter has two forms: data-correlated and periodic. As the name suggests, data-correlated jitter occurs when certain patterns of data are present. Periodic jitter, on the other hand, is cyclical – it has a defined frequency. Over a single period (1/F where F = frequency), clock signals stretch and shrink even though the elapsed time over a measurement period remains stable.
Random jitter, which impacts on a DAC’s SNR, can also be modelled. As one might expect, random jitter must be low to realise good SNR performance. Improvements are hard to realise as significant reductions in jitter are needed before there is any perceptible change. Another important parameter is the sampling frequency (Fs). The higher the value of Fs, the higher the SNR – doubling Fs improves SNR by 3 dB. (This has been inferred from Burr Brown’s very conservative formula for calculating a DAC’s SNR.)
Periodic jitter has, by definition, a defined frequency and its distortion effects can also be modelled. DACs (and ADCs) create distortion (sideband noise) when subject to periodic jitter. For a given input frequency, the side bands can be seen on either side of the fundamental, distanced by the jitter frequency. This is shown in fig 3.1:
Figure 3.1 Periodic jitter (Jpp) of 7 ns at 3kHz for a 10 kHz pure input tone. There are sidebands of 7 and 13 kHz whose distance from the fundamental is given by the jitter frequency (here, 3 kHz). Julian Dunn noted that ‘In this figure there are also "skirts" to the spectrum closer to the 10 kHz component. These are due to some low-frequency noise-like jitter in the system’.
While the graphic shows sine-wave periodic jitter affecting a 10 kHz audio tone, square wave jitter is even more harmful as it gives rise to continuous sidebands throughout the audio band. The strength of these is determined using Dunn’s formula:
Figure 3.2 Sideband energy levels increase with higher audio frequencies and higher jitter levels (J as in Jpp). Note wi refers to: F2π where F is the audio input frequency. (This is called the angular frequency). For example, Jpp at 7ns acting on an input tone of 10 kHz gives sidebands at -79.2db (as in figure 3.1).
wi refers to F [input audio frequency] x 2π, also called the angular frequency. For example, Jpp at 7 ns acting on an input tone of 10 kHz gives sidebands at -79.2db.) The formula reflects how sideband energy levels increase as frequencies and jitter levels rise. In plain terms, it means that the higher the input frequency and the higher the jitter, the greater the strength (or energy) of the sideband distortions.
Periodic jitter is more offensive than random jitter as its sidebands are not related to the harmonics of the tone being reproduced (i.e. they are ‘aharmonic’). Since any musical note’s harmonics extend well into the high frequencies, the sound of a decaying tone is distorted by periodic jitter: its ‘bloom’ is lost. Jitter is most damaging at high frequencies, i.e. when large voltage swings occur (slewing) as it leads to greater signal amplitude errors.
However, there is more to jitter than just its random or periodic modes. Other forms, all of which affect audio quality (and have the potential to cause sync lock issues), include:
The critical point is that jitter is a cumulative phenomenon: whatever its sources, they combine in a pernicious manner that always increases jitter levels overall. Collectively, this affects the sample clock at the DAC or ADC chip, which is where signal conversion occurs and distortion arises. The result is signal amplitude errors. While DACs and ADCs use several clock signals, it is jitter in the sample clock (LRCK) that is most detrimental to their performance. Fig 3.3 shows AKM’s AK4358VQ (as used on the Juli@ soundcard).
Figure 3.3 Pin layout of the AKM DAC chip. It offers eight output channels (four L-R pairs). Digital data input (at bit level) is on pins 13 to 16, the clock pins are 17 (LRCK), 10 (MCLK) and 9 (BICK). AKM calls MCLK the Master Clock. It is synchronized to LRCK (the most important, often referred to as the sample or word clock). AKM uses MCLK to operate its interpolation filter and delta/sigma modulator. (Ignore the pins marked DSD.)
Figure 3.4 A timing diagram for the AKM DAC chip (PCM default mode) showing LRCK (the sample clock) where one cycle is 1/Fs (the sampling frequency) and BICK (the bit-level clock, similar to an SPDIF signal. Where data are upsampled to 24/96, BICK runs at 6.144 mHz.
The sample clock determines when a sample (left and right pair) is dispatched. Timing errors mean that the signals are processed out of time so that their amplitudes are wrong. That is jitter distortion.
Random jitter is rare – it is almost always periodic. This is the worst kind of jitter but Phase Locked Loops (PLLs) are excellent at removing it. No matter what the system configuration is (single box, Transport/DAC, etc), there will be PLLs hard at work. Unfortunately, however, they can only work above a defined ‘cut-off’ frequency, often 1 kHz. They cannot remove jitter below this cut-off.
One could argue that designers should seek to shift jitter energy to higher frequencies to enable PLLs to work more effectively were it not that high frequency jitter has aliases and images of its own that appear below the cut-off.
As jitter is almost always periodic, it can, for a given input tone (pure sine wave), be modelled. Periodic jitter can be pictured as a tiny oscillator ‘beavering away’ at the DAC’s sample clock, constantly changing its accuracy by inducing phase or edge errors, shifting the clock phase by a small amount in time. This jitter error is given by:
In simple English, the formula says that the sample clock’s jitter (phase error) is cyclical and, at its worst, is half of Jpp (either adding to or subtracting from the length of the clock phase). Over a full cycle, the sample clock maintains accuracy as there are phases where the clock signal intervals are longer and others where it is shorter. (This is the nature of the Sin function.) The following parameters can thus be calcuated:
Dunn provides the formula for modelling jitter distortion for a given Jpp and Jf when applied to an input sine-wave tone. A program was used to generate wav files implementing this formula and providing 16- or 24-bit tones at any sampling frequency and either pure or afflicted with periodic jitter. (Basic dithering and 3rd-order noise shaping were applied.)
Figure 3.5 The spectrum of a 24/96 10 kHz software-generated tone with jitter modelled at 7 ns/3 kHz. Compare this to fig 1 which depicts a real 10 kHz tone with the same jitter. The model’s prediction is accurate, showing sidebands 6 kHz apart (at 7 and 13 kHz) at similar levels. (The fequency axis is logarithmic. The spectra in this manual were captured with the RMAA spectrum analyser using an FFT resolution of 0.37 Hz).
Thus, by recording a DAC’s analogue outputs for a given pure input tone, its overall jitter performance can be measured: the level and the position of the sidebands provide precise measures of Jpp and Jf for the transport/DAC combination. (Jf is obtained by examining the spectral view and Jpp is calculated from the sideband level using formula 3.2.)
The method provides insights into the overall jitter performance of a transport/DAC combination, including elusive variables such as the DAC’s effectiveness in rejecting jitter in the transport’s signal, the complexities of interface jitter or the effect of using a glass-fibre Toslink, and does so without having to resort to complex clock-signal analysis techniques such as eye-diagrams. Ideally, a high resolution DSO would be used but a cMP transport acting as a digital sampling oscilloscope (DSO) offers 24-bit resolution and 384 kHz bandwidth. Three test files were generated with the results shown below.
Figure 3.6 Software-generated 24/96 wav files were used to measure jitter at frequencies of 7 kHz (left), 3 kHz (centre) and 14 kHz (right) with simulated jitter at 7 ns (3kHz). The 14 kHz test is designed to demonstrate the three tones (11, 14 & 17 kHz) being recreated at the DAC's output. If this excessive jitter distortion was introduced by the ADC, it will be visible at the DAC's output.
Tests were conducted to measure the jitter component of a cMP-configured transport connected to a dCS Scarlatti DAC. The transport, fitted with an RME HDSP 9652 soundcard, fed 24/96 data via a glass-fibre Toslink to the DAC and provided the master clock (i.e. DAC was slaved).
The analogue output signal was recorded using a second cMP-configured machine fitted with an ESI Juli@ soundcard by connecting the DAC’s analogue output via low-capacitance (25 pF) Sommer Cable to the Juli@’s TRS (balanced) inputs. Both machines had high-quality power cords, line filtration and independent mains supplies. Cubase LE recording software was set to record stereo at 24/96. XP’s winlogon was reinstated to enable Cubase – see chapter 14 but the configuration was otherwise as per cMP specifications.
To test the recording device, analogue outputs of a normal computer’s on-board audio (Realtek ALC888 offering a 97dB SNR) was also measured. This showed all kinds of noise components and other artifacts. Given that the computer was setup for performance, not audio, this is to be expected.
Output from the Scarlatti DAC using a 7 kHz test tone is shown in fig 3.7.
Figure 3.7 The 7 kHz test tone as presented at the DAC’s outputs (filter 2). The overall noise floor is now at about -140 db with harmonics of the fundamental at 14, 21, 28 and 35 kHz. Jitter components no doubt exist but they are buried in the noise floor.
Figure 3.8 Sideband noise increases with frequency so a 14 kHz tone should be more revealing of jitter. This proved to be the case. The 2 kHz component is at a very low -135.5db, yielding a Jpp of just 11 ps but higher jitter levels are visible in the close-up.
Figure 3.9 Jitter levels are visible when looking at 3.8 in close-up.
A single jitter sideband component of over -130db would translate to over 20 ps Jpp. No such component is visible in the above traces but individual jitter components can be seen from figure 3.8 & 3.9 (14kHz input tone) as follows:
This yields an overall Jpp RSS of 51 ps.
Although extended listening had suggested that cMP exhibited low jitter, it was never imagined that Jpp values as low as 51 ps would be achieved. Equipment reviews in Stereophile, for example, report jitter levels of around 200 ps and only occasionally report on equipment with jitter levels below 200 ps. Even these are well above 100 ps.
The finding explains why the Scarlatti Clock failed to impress: the added complexity of the device by way of an extra power supply and clock sync circuitry and to the fact that the circuit was no longer galvanically isolated combined to inject noise that made its way to the DAC’s sample clock – measuring jitter with the Clock in place shows a 4 ps increase in Jpp. That said, the Scarlatti DAC most certainly does impress in this context.
Perhaps the most interesting insight gained from the measurement cycle is that jitter problems are not necessarily resolved by ‘polishing’ the sample clock. That is to treat the symptom, not the cause. There is no doubt the Scarlatti Clock offers superb accuracy and low jitter but crystal oscillators (XOs) already offer outstanding stability and, more important, jitter as low as 20 ps. It is pollutants like power supply noise that destabilise them and lead to poor performance.
Transports based on spinning CDs inevitably destabilise an XO clock. In that context, clock treatments as advocated by dCS have a useful role. This does not hold true for Computer Transports.
While issues of power supply quality are well understood and significant progress is being made, there is more to consider. Fig 3.3, for example, shows a typical DAC chip. A seemingly perfect sample clock entering the chip after exhaustive treatment is still subject to noise on the chip’s other inputs. At the microscopic level, DACs are complex integrated circuits whose sample clock is not galvanically isolated. Noise from the data and other clock pins can easily impact on the sample clock. With DACs becoming ever more complex and with ever higher levels of sample buffering, this type of contamination looks set to grow. In other words, every pin needs polishing.
In a Computer Transport, parameters like RAM settings, RAM quality and motherboard traffic all make a perceptible difference. The purity with which data is streamed to the DAC is critical. It is here that cMP excels – measurably.